SemiAnalysis measured the Kirin 9030's metal pitch at 32.5nm. That beats Intel 18A by roughly 10% — and it was done without EUV.
Key facts
- Kirin 9030 metal pitch: 32.5nm.
- Intel 18A metal pitch: ~36nm (est. 10% larger).
- SMIC lacks EUV; uses DUV lithography.
- Chip powers Huawei's newest flagship phone.
SemiAnalysis published electron microscope images of HiSilicon's Kirin 9030, the chip inside Huawei's latest flagship phone. According to @SemiAnalysis_, the smallest metal pitch measures 32.5 nanometers. That is tighter than Intel 18A, their brand new leading edge node. A Chinese fab with no EUV is out-pitching Intel's EUV node by roughly 10 percent.
The result is surprising because SMIC, the fab that likely produces the Kirin 9030, is under US export controls that block access to ASML's EUV tools. Instead, SMIC uses deep ultraviolet (DUV) lithography, which has lower resolution. The 32.5nm pitch implies that SMIC has pushed DUV multipatterning beyond what most industry observers considered possible. Intel's 18A node, by contrast, uses EUV and is Intel's most advanced process, targeting Panther Lake processors.
SemiAnalysis notes that "a Chinese fab, cut off from the most advanced tools, without EUV, is packing its wires about ten percent tighter than Intel's leading edge EUV node." The finding raises questions about the effectiveness of export controls and whether SMIC has developed novel patterning techniques. It also puts pressure on Intel's process roadmap, which has already faced delays.
How SMIC might be doing it
Achieving 32.5nm metal pitch with DUV requires aggressive self-aligned quadruple patterning (SAQP) or similar multi-patterning schemes. Typically, DUV's resolution limit is around 38-40nm for metal pitch with SAQP. SMIC may have improved overlay accuracy or used novel spacer materials to push below 35nm. The exact method is not disclosed, and SemiAnalysis did not provide a full process analysis.
Implications for the chip war
The Kirin 9030 result suggests that export controls on EUV are not a complete chokehold. If SMIC can approach Intel 18A density with DUV, the gap between Chinese and Western fabs may be narrower than assumed. However, metal pitch is only one metric; transistor performance, power, and yield remain unknown. Huawei and SMIC have not commented on the measurement.
What to watch
Watch for independent verification of the 32.5nm pitch by TechInsights or other reverse-engineering firms. Also watch for Intel's 18A yield disclosures in Q2 2026 earnings calls — if Intel cannot demonstrate clear density and performance advantages, the narrative of US process leadership weakens.
[Updated 21 Jul via tomshardware]
Tom's Hardware reports that SMIC's N+3 process achieves a transistor density of approximately 52 million transistors per square millimeter, comparable to TSMC's N6 node [per Tom's Hardware]. However, the node reportedly fails to deliver competitive performance or power efficiency, suggesting the density gain comes with trade-offs.
