A team from MITRE, CU Boulder, Sandia, Arizona, and MIT published the first fully monolithic CMOS platform for piezo-optomechanical photonic integrated circuits (POMPICs) in July 2026. The work, detailed on arXiv, achieves wafer-scale integration of photonic and electronic layers on a single chip, eliminating the hybrid assembly that has limited prior optomechanical systems.
Key facts
- First fully monolithic CMOS platform for piezo-optomechanical photonics.
- Wafer-scale integration on electronic backplane demonstrated.
- 2.3x reduction in insertion loss vs. hybrid equivalents.
- 40% bandwidth improvement, up to 4.8 GHz.
- Published on arXiv July 2026; 5 institutions involved.
Researchers from MITRE, University of Colorado Boulder, Sandia National Laboratories, University of Arizona, and MIT have demonstrated what they call the first "fully monolithic, all-CMOS fabricated platform" for piezo-optomechanical photonic integrated circuits. The paper, titled "Monolithic Integration of Piezo-Optomechanical Photonics and CMOS Electronics" and published on arXiv in July 2026, shows "wafer-scale integration of POMPICs on an electronic backplane."
What the platform does
Piezo-optomechanical photonics uses piezoelectric materials to mechanically deform optical waveguides, enabling on-chip modulation, filtering, and switching. Until now, such devices required separate fabrication of the photonic layer and the CMOS control electronics, then bonding them together — a process that limits yield, increases cost, and constrains scaling. The MITRE-led team eliminated that step by building the entire stack in a standard CMOS foundry, using a custom process that deposits and patterns piezoelectric thin films directly atop the CMOS backplane.
The paper reports that the monolithic approach yields a 2.3x reduction in insertion loss compared to hybrid-integrated equivalents at the same operating wavelength (1,550 nm), and a 40% improvement in electro-optic bandwidth (up to 4.8 GHz). The authors attribute this to the elimination of parasitic capacitance from bond pads and interconnects between the photonic and electronic layers. [According to the source]
Why this matters for AI and data centers
The unique angle here is not just the engineering milestone — it is the implication for interconnects in large-scale AI systems. Optical interconnects are increasingly critical for scaling GPU clusters beyond the rack level, but current solutions rely on discrete photonic engines that add latency and power overhead. A monolithic CMOS-POMPIC platform could eventually integrate high-speed optical modulators directly into the same die as the logic, shrinking the physical distance between compute and photonics to the micron scale.
MIT, one of the collaborating institutions, has previously partnered with Anthropic and Google on AI infrastructure research [per KG entity relationships]. While this specific paper does not mention AI workloads, the timing is notable: data-center optical interconnect spending is projected to exceed $8 billion in 2026, and any process that reduces the cost or complexity of photonic integration has direct relevance to that market.
Limitations and next steps
The paper is a proof-of-concept demonstration on a 200 mm wafer; the authors do not disclose yield statistics or power consumption figures for the full system. They note that the piezoelectric thin-film deposition step currently requires a custom tool modification, which may limit immediate foundry adoption. The team plans to release a detailed process design kit (PDK) for the platform in Q4 2026. [According to the source]
What to watch
Watch for the Q4 2026 release of the process design kit (PDK) for this platform. If foundry partners adopt the custom piezoelectric deposition step, the first monolithic POMPIC-based optical interconnects could appear in AI accelerator test chips by mid-2027.
Source: semiengineering.com
