Huawei chairman Xu Zhijun publicly thanked US sanctions for enabling China's semiconductor growth. His remarks accompanied a technical roadmap targeting 1.4nm-equivalent density by 2031 using a novel scaling approach.
Key facts
- Huawei chairman Xu Zhijun publicly thanked US for sanctions.
- Tau Scaling Law targets signal speed, not transistor size.
- LogicFolding cuts redundant buffers by more than 50%.
- Target density comparable to 1.4 nm by 2031.
- China still faces gaps in yield, power, tooling, and scale.
Huawei chairman Xu Zhijun turned US chip controls into a narrative of Chinese resilience, stating, 'We are also grateful to the US for enabling our country's semiconductor industry chain to truly grow' [According to @rohanpaul_ai]. The remark, reported via social media and huaweicentral.com, frames sanctions as a strategic catalyst rather than a chokehold.
Tau Scaling Law and LogicFolding
Huawei's technical countermove is the Tau Scaling Law, which redefines the optimization target from transistor miniaturization to signal propagation speed. 'Modern chips often lose speed inside long wires, timing buffers, and layout delays rather than inside the transistor itself,' the company explained. The approach abandons the traditional race for smaller nodes in favor of reducing interconnect delays.
The enabling technology, LogicFolding, stacks logic in 3D to shorten signal paths. Huawei claims this method 'reportedly cutting redundant buffers by more than 50%,' increasing density without relying on restricted extreme ultraviolet (EUV) lithography machines [According to @rohanpaul_ai]. The company projects this path could achieve density comparable to 1.4 nm by 2031.
The Structural Gap
This is not a substitute for TSMC-style leading-node manufacturing. China still faces 'hard gaps in yield, power efficiency, tooling, and global production scale,' as the source notes. The Tau Scaling Law is a design-side optimization, not a fabrication breakthrough — it does not eliminate the need for advanced lithography or process control.
The unique take: Huawei is effectively redefining the metric of semiconductor progress from 'node size' to 'signal latency per watt,' a shift that makes its design achievements look more competitive against TSMC's 3nm-class processes than they actually are. Until yield data emerges, this remains a paper advantage.
What to watch
Watch for Huawei's 2026 annual chip roadmap update, expected in Q4, which should disclose LogicFolding yield data and power efficiency benchmarks. Also monitor whether TSMC or Samsung adopts similar interconnect-first scaling in their 2027 node roadmaps.
