Cerebras Systems is keeping its next-generation CS4 wafer-scale chip on 5nm, per @SemiAnalysis_. The decision stems from SRAM scaling stagnation that makes a 3nm node migration ineffective.
Key facts
- CS4 stays on 5nm process node
- SRAM scaling has flattened across nodes
- CS-2 has 40 GB SRAM, 850,000 cores
- 3nm offers only ~5-10% SRAM density gain
- CS-2 achieves 20 PB/s memory bandwidth
Cerebras Systems is keeping its next-generation CS4 wafer-scale chip on 5nm, per @SemiAnalysis_. The decision stems from SRAM scaling stagnation that makes a 3nm node migration ineffective.
The SRAM Scaling Problem
The core issue is that SRAM bit-cell density has effectively ceased scaling with process nodes. [According to @SemiAnalysis_], moving to 3nm does not magically fix this. For a chip architecture like Cerebras' that relies on massive on-chip SRAM—the CS-2 packs 40 GB of SRAM across 850,000 cores—the memory density per square millimeter matters more than transistor speed. Without SRAM density gains, a node shrink would increase logic density and reduce power but leave the chip's memory-limited throughput largely unchanged.
This echoes broader industry trends. TSMC's N3 node offers only ~5-10% SRAM density improvement over N5, far below historical 30-50% node-over-node gains [industry data]. For Cerebras, which fabricates a single 46,225 mm² wafer-scale chip, the cost of a new mask set and yield learning curve on 3nm likely outweighs the marginal SRAM benefit.
Architectural Implications
Cerebras' competitive advantage lies in eliminating off-chip memory bandwidth bottlenecks by placing all memory on-die. The CS-2 achieves 20 PB/s memory bandwidth. Sticking with a mature 5nm process (likely TSMC N5P or N4) allows Cerebras to optimize yield and reduce per-wafer cost while maintaining SRAM capacity. Competitors like NVIDIA and AMD, which use HBM3 off-chip memory, benefit more from 3nm's logic density improvements for compute units. Cerebras, by contrast, is SRAM-bound.
What This Means for the Market
The CS4's 5nm choice signals that wafer-scale AI chips face a different scaling calculus than conventional GPUs. While NVIDIA's B200 Blackwell moves to TSMC 4NP (a 5nm-class node), the CS4's rationale is distinct: it is not about compute density but memory architecture. This could widen Cerebras' advantage in workloads sensitive to memory bandwidth and latency, such as sparse transformer inference and scientific simulation.
Key Takeaways
- Cerebras CS4 stays on 5nm due to SRAM scaling flattening, per @SemiAnalysis_.
- 3nm offers no density gain, so the chip prioritizes yield and cost.
What to watch
Watch for Cerebras' official CS4 announcement, expected in H2 2026, for specific SRAM capacity and performance metrics. Also track TSMC's N3P SRAM density data—if it improves beyond current projections, Cerebras may reconsider for CS5.
