Google selected Intel's EMIB-T packaging for its 9th-generation TPU, codenamed Humufish, breaking a decade-long reliance on TSMC's CoWoS-L. The decision, reported by SemiAnalysis, signals the first major defection from TSMC's dominant advanced packaging ecosystem for high-performance AI chips.
Key facts
- Google booked Intel to package 3 million TPUs by 2028
- EMIB-T uses TSVs for vertical power delivery
- CoWoS-L scales to 5.5X reticle size today
- TSMC promises 14X reticle scale by 2030
- Google used CoWoS since 3rd-gen TPU
Google has been a loyal TSMC CoWoS customer since the Third-Generation TPU, migrating from CoWoS-S to CoWoS-L for its 7th- and 8th-generation chips. CoWoS-L uses a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges, scaling packages to 5.5X the reticle size. TSMC promises 14X reticle scale by 2030 According to the source.
Key Takeaways
- Google picks Intel EMIB-T for 9th-gen TPU, breaking TSMC CoWoS monopoly.
- Move signals architectural bet on power integrity and reticle-free scaling.
Why EMIB-T Won
Intel's EMIB technology dispenses with interposers entirely, embedding tiny silicon bridges in an organic substrate only where high-density die-to-die links are needed. EMIB-T adds through-silicon vias (TSVs) for vertical power delivery, plus metal-insulator-metal (MIM) capacitors and a dedicated ground plane to improve power integrity. The latter is critical for next-gen AI accelerators, where power delivery is becoming as challenging as signal routing.
This isn't a supply-constrained stopgap. Google's 3 million TPU packaging booking with Intel, reported by our KG intelligence [per SemiAnalysis], suggests a strategic bet on EMIB-T's architectural advantages, not just a hedge against TSMC capacity. CoWoS-L's interposer reticle limits still constrain package size, while EMIB-T scales by adding bridges without reticle penalties.
The Competitive Landscape
TSMC's CoWoS remains the de facto standard for nearly all AI and HPC processors, but Google's switch validates Intel's foundry services in advanced packaging. The move also pressures TSMC to accelerate CoWoS-L reticle scaling promises. If EMIB-T delivers on power integrity for Google's massive TPU deployments, other hyperscalers may follow.
Google's 8th-gen TPUs already use CoWoS-L, and switching packaging technologies mid-generation is complex. SemiAnalysis's report indicates Google is willing to absorb those risks for Humufish, likely targeting 2028-2029 deployment windows.
What to watch
Watch for TSMC's response at its 2027 Technology Symposium: whether it accelerates CoWoS-L reticle scaling to 10X+ and whether it introduces competitive TSV-in-bridge packaging. Also track whether Amazon or Meta make similar EMIB-T commitments for their next-gen AI chips.
Source: tomshardware.com
