advanced packaging
30 articles about advanced packaging in AI news
Nvidia B200 Costs $6,400 to Produce, Gross Margin Hits 82%
Epoch AI estimates Nvidia's B200 GPU costs $5,700–$7,300 to produce, with HBM memory and advanced packaging accounting for two-thirds of the cost. At a $30k–$40k sale price, chip-level gross margins reach ~82%, though rack-scale margins may be lower.
Alibaba's Qwen 3.5 Omni Targets Western Market with Advanced Voice AI and Strategic Messaging
Alibaba's Qwen 3.5 Omni model features a robust voice AI that handles interruptions naturally, while its launch presentation signals a direct push to compete in Western markets as a cost-effective alternative.
Intel EMIB-T Wins Second Cloud ASIC, Early 2028 Production
Intel EMIB-T wins second cloud ASIC project; MediaTek CEO confirms early 2028 production on track despite packaging yield and capacity challenges.
China PLP System Passes Validation at 510×515mm Panel Size
CFMEE validated a 510×515mm PLP system for AI chip packaging, challenging TSMC and Intel. The system targets HBM and AI accelerators, with potential 30% cost savings.
Google TPU Humufish Drops TSMC CoWoS for Intel EMIB-T
Google's next TPU Humufish uses Intel EMIB-T packaging instead of TSMC CoWoS, breaking the industry default for AI accelerators.
Nvidia Commits $6.5B to Photonics in Supply Chain Bet on AI's Next Bottleneck
Nvidia has invested over $6.5 billion across four photonics suppliers since March 2026, pairing equity stakes with multi-billion-dollar purchase commitments. The deals coincide with capacity expansion announcements from Coherent, Nokia, and Japan's JX Advanced Metals, and signal that optical interco
Foxconn to Mass-Produce 10,000+ CPO Optical Switches for AI in Q3 2026
Foxconn's manufacturing arm will begin volume production of advanced co-packaged optics (CPO) switches in Q3 2026, targeting over 10,000 units. This move directly addresses the critical bandwidth and power bottlenecks in next-generation AI data center infrastructure.
TSMC's $56B 2026 CapEx Fuels AI Chip Race with 22 New Fabs
TSMC is constructing up to 22 advanced semiconductor fabs simultaneously, backed by a $52–56 billion capital expenditure plan for 2026. This unprecedented manufacturing scale is critical for producing the 2nm-and-below chips required by next-generation AI models.
The Invisible Dance: How AI Chip Manufacturing Relies on Microscopic Wire Bonding
High-speed semiconductor wire bonding creates thousands of electrical connections per minute using ultra-fine 25-micron wires. This critical but often overlooked process enables the AI chips powering today's most advanced systems.
China's DFSX SuperNode Doubles GB200 Memory Bandwidth on 14nm
China's DFSX SuperNode claims 2x GB200 memory bandwidth using 14nm vertical towers, but lacks benchmarks or ship dates, warranting skepticism.
MediaTek Targets $2B AI Chip Sales, $80B Custom ASIC Market
MediaTek projects $2B+ AI chip sales in 2026, targets 15-20% of an $80B custom ASIC market by 2027, backed by a $5B board-approved supply chain investment.
Samsung Wins $200B Broadcom AI Chip Deal, Foundry Bet Pays Off
Samsung wins $200B Broadcom AI chip deal, boosting foundry push against TSMC. Partnership covers custom AI chips for data centers.
China Blank-Checks Huawei for Inference Chip Push
China is giving Huawei a blank check for inference chips, per a tweet by Natolambert on February 3, 2026, shifting focus from training to inference.
TSMC Pledges Extra $100B for Arizona, Total US Investment Hits $265B
TSMC pledged $100B more for Arizona fabs, total US investment $265B, driven by AI chip demand. Net income surged 77% to $22B in Q2.
Google Chooses Intel EMIB-T for 9th-Gen TPUs, Breaking TSMC's CoWoS Monopoly
Google picks Intel EMIB-T for 9th-gen TPU, breaking TSMC CoWoS monopoly. Move signals architectural bet on power integrity and reticle-free scaling.
Cerebras, Flex Expand CS-3 Production 7x at Milpitas Facility
Cerebras and Flex expand CS-3 production 7x at Milpitas facility. The partnership keeps wafer-scale AI manufacturing in the U.S. as Nvidia faces delays.
Nvidia's Next-Gen AI Rack Delayed to 2028, SemiAnalysis Says
Nvidia's next-gen AI rack delayed to 2028 on manufacturing snags per SemiAnalysis. Delay benefits AMD and custom silicon rivals.
Qualcomm Taps TSMC for 3nm/2nm Dragonfly C100 CPUs, AI300 Accelerators
TSMC to fab Qualcomm's Dragonfly C100 and AI300 chips on 3nm/2nm nodes. The move challenges NVIDIA in data center AI, but timelines and performance remain undisclosed.
Google Open-Sources DiffusionGemma, 26B Model Hits 1K Tokens/Sec on H100
Google open-sourced DiffusionGemma, a 26B-parameter diffusion text model hitting 1,000 tokens/sec on H100 — 4x faster than autoregressive models, but with lower quality.
Google Books Intel for 3M+ TPUs in 2028 as TSMC CoWoS Hits Capacity Wall
Google booked Intel to package 3M+ TPUs in 2028 as TSMC CoWoS capacity caps out. SK hynix tests HBM on Intel EMIB, potentially unlocking Nvidia's Feynman architecture.
MLCC Shortage Threatens AI Server Ramp: Prices Hiking, Lead Times Stretching
MLCCs, cheap components stabilizing voltage in AI servers, face supply crunch as demand grows ~5x by CY27. Lead times stretch, prices hike, new lines take 2 years.
CNAS Report: AI Hits Silicon Wall as Chip Supply Trails $700B CapEx
CNAS report warns semiconductor manufacturing cannot keep pace with AI demand as hyperscalers plan $700B+ CapEx in 2026. Silicon replaces power as the near-term constraint.
GUC, Wiwynn Partner on Silicon-to-System AI Infrastructure for Hyperscalers
GUC and Wiwynn partner on silicon-to-system AI infrastructure, integrating SoC design, optical I/O, and liquid cooling for hyperscalers.
The $500B AI Chip Bottleneck: One Material, One Supplier
A single Japanese chemical company supplies 98% of the thin-film material used in every AI chip on earth. NVIDIA is paying half the capex to expand supplier fabs as lead times stretch past 6 months.
Intel's UCIe-S Hits 48 Gb/s on 22nm, Beats 3nm EMIB
Intel demonstrated a UCIe-S die-to-die interconnect on 22nm hitting 48 Gb/s/lane over standard organic substrate, beating a 3nm EMIB design with 3× higher data rate and 2.8× higher bandwidth density. This signals a strategic shift away from EMIB for Intel's own products toward UCIe over substrate.
Jensen Huang's 30-Year TSMC Battle: From 3D Graphics to AI GPUs
A 30-year-old comic shows Jensen Huang convincing TSMC to supply wafers for 3D graphics chips. Today, he's still fighting for wafer supply, but now for AI GPUs, alongside Broadcom, AMD, MediaTek, and Amazon.
AI Chip Capacity Crisis: 10GW Left Through 2030, Prices Up Double Digits
The AI accelerator market has only 10 gigawatts of capacity left for contract through 2030, with 100GW already under contract. Prices are rising double digits as one competitor has stopped taking orders entirely.
Microsoft's Fairwater AI Data Center Launches Early, Boosts Azure Capacity
Microsoft has launched its Fairwater AI data center ahead of schedule. The facility adds significant high-performance computing capacity to Azure's AI infrastructure, crucial for training and running large models.
Nvidia Invests $2B in Marvell to Expand NVLink Fusion Chip Partnership
Nvidia is investing $2 billion in Marvell Technology to deepen their partnership on NVLink Fusion, a chip-to-chip interconnect crucial for scaling AI training clusters. This strategic move aims to secure supply and accelerate development of high-bandwidth links between GPUs and custom AI accelerators.
Aehr Test Systems Lands $41M AI Chip Order; H2 Bookings Top $92M
Aehr Test Systems received a record $41 million production order from a key hyperscale AI customer. Total bookings for the second half of its fiscal year exceeded $92 million, highlighting surging demand for semiconductor test and burn-in equipment.