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TSMC, Intel, Samsung, GF Split on Co-Packaged Optics

Four foundries—TSMC, Intel, Samsung, GlobalFoundries—are pursuing distinct co-packaged optics strategies as electrical interconnects fail beyond 200-400 Gb/s per lane. The approaches are not directly comparable, reflecting divergent packaging bets.

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Source: tomshardware.comvia tomshardwareSingle Source
How are TSMC, Intel, Samsung, and GlobalFoundries approaching co-packaged optics for AI scale-up connectivity?

TSMC, Intel, Samsung Foundry, and GlobalFoundries have each announced distinct co-packaged optics (CPO) manufacturing strategies, moving optical engines onto processor packages as electrical interconnects fail to scale beyond 200-400 Gb/s per lane. The four approaches are not directly comparable, reflecting different packaging, laser, and integration choices.

TL;DR

Four foundries pursue distinct CPO strategies · CPO moves optics onto processor package · 200-400 Gb/s lanes drive optical shift

TSMC, Intel, samsung-foundry" class="entity-chip">Samsung Foundry, and GlobalFoundries have each staked out four distinct co-packaged optics (CPO) roadmaps, per Tom's Hardware. None of the four strategies are directly comparable, reflecting divergent bets on packaging, lasers, and integration depth.

Key facts

  • Four foundries: TSMC, Intel, Samsung Foundry, GlobalFoundries
  • CPO targets 200-400 Gb/s per lane signaling
  • Intel EMIB-T won second cloud ASIC, early 2028 production
  • TSMC CoWoS underpins Nvidia Blackwell and Vera Rubin
  • Dozens of companies active in CPO ecosystem

The CPO race is about to begin, and the four foundries that actually manufacture chips are taking four different paths. Electrical interconnects are no longer scaling as quickly as AI processors, and feeding thousands of accelerators within a data center requires an exponential increase in communication bandwidth According to Tom's Hardware.

Why copper is dying at the package edge

In a traditional optical networking architecture, the processor or switch ASIC communicates electrically with a pluggable optical transceiver located at the front panel of a server or switch. As signaling speeds climb to 200 Gb/s - 400 Gb/s per lane and beyond, transmitting electrical signals over long copper PCB traces on a motherboard becomes increasingly inefficient due to higher insertion loss, greater power consumption, and tighter signal integrity requirements. While technically possible, it demands better materials, retimers, complex compensation processing, and equalization circuitry, which increases infrastructure cost and power consumption.

CPO moves optical engines next to the processor or switch ASIC to shorten the electrical path before signals are converted into light. The result: lower power consumption per transmitted bit, increased bandwidth density, and predictable scalability. CPO is increasingly viewed as a necessary technology for next-generation AI infrastructure.

Four foundries, four bets

Only four foundries have publicly articulated meaningful CPO manufacturing strategies: Intel Foundry, GlobalFoundries, Samsung Foundry, and TSMC. Each represents a different strategy, and their plans and capabilities may not be directly comparable.

Intel's approach builds on its EMIB-T packaging technology, which the company has already leveraged to win a second cloud ASIC project with early production targeted for 2028 [per our prior reporting]. TSMC, by contrast, is extending its CoWoS packaging family, which currently underpins Nvidia's Blackwell and Vera Rubin GPU lineups. Samsung Foundry and GlobalFoundries have each articulated their own integration paths, though the source does not disclose specific packaging names or timelines for either.

Because AI is viewed as a major megatrend, CPO is set to become ubiquitous; dozens of companies work in the CPO ecosystem, including foundries, OSATs, optical I/O startups, laser manufacturers, fiber suppliers, packaging houses, and networking vendors. The source limits its analysis to the four companies that actually produce things and whose roadmaps reflect their technological capabilities.

What the source doesn't say

The Tom's Hardware piece does not disclose specific power-per-bit numbers, bandwidth-density metrics, or target production dates for any of the four foundries' CPO offerings. It also does not name which laser or fiber suppliers each foundry has partnered with. Those gaps matter: CPO's viability hinges on laser reliability and yield, which historically have been the hardest problems to solve at scale.

Key Takeaways

  • Four foundries—TSMC, Intel, Samsung, GlobalFoundries—are pursuing distinct co-packaged optics strategies as electrical interconnects fail beyond 200-400 Gb/s per lane.
  • The approaches are not directly comparable, reflecting divergent packaging bets.

What to watch

Watch for the first production CPO design win announcement, likely from TSMC or Intel, and whether either foundry discloses power-per-bit improvements versus pluggable transceivers. Intel's EMIB-T second cloud ASIC, targeted for early 2028 production, is the earliest concrete CPO-related milestone on the calendar. A laser-supplier partnership disclosure would signal manufacturing readiness.

Spectrum-X CPO Switch Tray


Source: tomshardware.com


Sources cited in this article

  1. PCB
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AI-assisted reporting. Generated by gentic.news from 3 verified sources, fact-checked against the Living Graph of 4,300+ entities. Edited by Ala SMITH.

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AI Analysis

The structural story here is that CPO has moved from academic curiosity to foundry-level competition, and the four strategies reflect fundamentally different business models. TSMC is extending CoWoS, its proven AI packaging workhorse that already carries Nvidia's Blackwell and Vera Rubin — a low-risk incremental play. Intel, by contrast, is betting on EMIB-T, a newer technology that has already won two cloud ASIC projects, suggesting Intel Foundry is using CPO as a wedge to win back AI customers from TSMC. The lack of comparable metrics is telling. None of the four foundries has disclosed power-per-bit or bandwidth-density numbers for their CPO offerings, which means the current race is about design wins, not measured performance. Intel's EMIB-T wins are the only public evidence of customer traction, but the source does not name the cloud customers — a significant omission given that hyperscalers are the primary buyers. The contrarian read: CPO's biggest risk is not packaging but lasers. The source notes that optical components' cost and complexity historically limited them to long-reach connections, and nothing in the foundry roadmaps addresses laser reliability at data-center scale. Until a foundry names a laser partner and discloses yield data, treat all four roadmaps as marketing claims.
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