interconnect
30 articles about interconnect in AI news
Google’s Virgo network interconnects 134K TPUv8t chips at 47 Pbps
Google's Virgo network interconnects 134,400 TPUv8t chips at 47 Pbps, targeting large-scale training clusters.
Nvidia Invests $2B in Marvell for NVLink Fusion Interconnect
Nvidia is investing $2 billion in Marvell Technology to deepen their partnership on NVLink Fusion, a new interconnect architecture for scaling AI clusters beyond current limits.
IOWN Forum Pushes All-Photonic WAN for AI Neocloud Interconnects
The IOWN Global Forum is focusing its optical networking tech on datacenter interconnects, aiming to let GPU 'neoclouds' and financial firms use cheaper, remote facilities without latency penalties for AI workloads.
AMD Backs UALink Open Interconnect to Challenge NVIDIA NVLink in AI
AMD is supporting the newly formed UALink Consortium, which aims to create an open standard for connecting AI accelerators. This move challenges NVIDIA's control over the critical NVLink technology that underpins its AI data center systems.
Ethernet AI Switch Sales Double, InfiniBand Rebounds 22% in Q2
Ethernet AI switch sales doubled YoY as InfiniBand rebounded 22%. Ethernet now captures 41% of AI interconnect revenue, up from 28%.
Nvidia Partners Corning for US Fiber Manufacturing, Prepaying Billions
Nvidia partners Corning for US fiber manufacturing with multibillion-dollar prepayments, increasing domestic capacity by 50%+ for AI GPU cluster interconnects.
AI Data Centers Face 220GW Grid Jam, Power Infrastructure Becomes Bottleneck
PJM's 220GW interconnection queue shows AI data center growth is now constrained by power grid capacity, not compute. Hyperscalers face 3-7 year delays.
Nvidia Invests $2B in Marvell to Deepen NVLink Fusion Tie-Up
Nvidia invested $2B in Marvell to deepen NVLink Fusion partnership, integrating Marvell custom silicon into AI interconnect fabric.
Intel's UCIe-S Hits 48 Gb/s on 22nm, Beats 3nm EMIB
Intel demonstrated a UCIe-S die-to-die interconnect on 22nm hitting 48 Gb/s/lane over standard organic substrate, beating a 3nm EMIB design with 3× higher data rate and 2.8× higher bandwidth density. This signals a strategic shift away from EMIB for Intel's own products toward UCIe over substrate.
Google's Virgo Network Links 134,000 TPU v8 Chips with 47 Pbps Fabric
Google unveiled its Virgo networking stack for TPU v8, capable of linking 134,000 chips in a single fabric with 47 petabits/sec of bi-sectional bandwidth. This represents a massive scale-up in interconnect technology for large-scale AI model training.
Cisco Reveals Scale-Across GPU Networking Needs 14x DCI Bandwidth
Cisco's chief architect detailed the massive bandwidth requirements for connecting AI clusters via 'scale-across' GPU networking, which needs 14x the capacity of traditional data center interconnects. This shift is creating a multi-billion dollar market for 800G coherent pluggables and deep-buffered switches.
UALink 2.0 Spec Finalized, Aims to Challenge NVLink for AI Clusters
The UALink 2.0 interconnect specification has been finalized, providing a standardized way to link AI accelerators from AMD, Intel, and others. However, it lags behind NVIDIA's established NVLink technology in real-world deployment.
Nvidia's Silicon Photonics Roadmap Targets AI Data Center Bottlenecks
Nvidia is developing its own silicon photonics-based interconnects to address the growing data transfer bottleneck within AI data centers and supercomputers. This move is critical as AI model size and cluster scale continue to grow exponentially.
Nvidia Invests $2B in Marvell to Expand NVLink Fusion Chip Partnership
Nvidia is investing $2 billion in Marvell Technology to deepen their partnership on NVLink Fusion, a chip-to-chip interconnect crucial for scaling AI training clusters. This strategic move aims to secure supply and accelerate development of high-bandwidth links between GPUs and custom AI accelerators.
Open-Source AI Crew Replaces Notion, Obsidian with 8 Local Agents
A researcher has built a fully local, open-source system of 8 specialized AI agents that work together to manage an Obsidian vault—handling notes, inboxes, meetings, and deadlines. It replaces separate tools like Notion and inbox triagers with an autonomous, interconnected crew.
Google Books Intel for 3M+ TPUs in 2028 as TSMC CoWoS Hits Capacity Wall
Google booked Intel to package 3M+ TPUs in 2028 as TSMC CoWoS capacity caps out. SK hynix tests HBM on Intel EMIB, potentially unlocking Nvidia's Feynman architecture.
OpenAI Eyes 10GW Ohio Data Center with Nvidia Backing
OpenAI is negotiating a 10GW Ohio data center with Nvidia backing, potentially costing $500B on federal land.
Google's 1 GW Texas AI Campus Tests 'Power-First' Model for Hyperscaler
Google's Texas AI campus tests a power-first model, pairing 1 GW generation with a data center to bypass grid constraints for AI infrastructure expansion.
Cerebras Reengineers Mechanical Playbook for Wafer-Scale Chip Cooling
Cerebras disclosed three mechanical innovations—vertical power delivery, flexible interposers, and direct-impingement cooling—to prevent wafer-scale chips from cracking, rewriting engineering fundamentals.
PJM Warns AI Data Center Load Could Break Power Market Assumptions
PJM warns AI data center load could grow 5x to 25 GW by 2035, colliding with queue delays and outdated market rules. Regulators flag reliability and cost risks.
Ayar Labs Joins NVIDIA NVLink Fusion Ecosystem for Co-Packaged Optics
Ayar Labs joined NVIDIA's NVLink Fusion ecosystem to bring co-packaged optics to AI factories, following its $500M Series E and alongside Lightmatter's similar move.
Dell Ships First Nvidia Vera Rubin NVL72 Rack to CoreWeave
Dell delivered the first Nvidia Vera Rubin NVL72 rack to CoreWeave. Each rack packs 72 Rubin GPUs, 36 Vera CPUs, 3.6 exaFLOPS FP4 inference, 75 TB memory, and 260 TB/s NVLink bandwidth.
Huawei Hits 1.5µm Bond Pitch in Kirin 2026 Chips, Beats TSMC
Huawei's 2026 Kirin chips achieve 1.5µm hybrid bonding pitch, 16-36x denser than TSMC. Next year targets 1µm.
Huawei Chairman Thanks US Sanctions, Claims 1.4nm Equivalent by 2031
Huawei chairman thanks US sanctions, unveils Tau Scaling Law targeting 1.4nm density by 2031 via signal-speed optimization, not transistor shrinking.
Blackwell NVLink Breaks Confidential Compute, 61% Regression Reported
NVIDIA Blackwell confidential computing disables NVLink multicast, causing 61% regression on SGLang Qwen3.5 397B. Hopper had unencrypted NVLink, compounding the issue.
ERCOT datacenter requests exceed grid capacity by 5x
ERCOT datacenter requests far exceed grid underwriting capacity, per @SemiAnalysis_, revealing grid approval as a binding constraint on AI infrastructure buildout.
AI Data Centers Hit Water Wall: 2M Gallons Per Day Per Campus
Water capacity is now a siting gatekeeper for AI data centers. A Virginia campus requested 2M gallons per day; Georgia told a 6 MGD project 'we just don't have the water.'
Huawei's τ Scaling Law Redefines Transistor Race Without EUV
Huawei's τ Scaling Law at IEEE ISCAS replaces geometric transistor scaling with time-based optimization, targeting 1.4nm density by 2031 without EUV, challenging US export controls.
Cerebras Hits 981 Tokens/sec on 1T-Parameter Kimi K2.6, Claims 6.7× GPU Cloud Speedup
Cerebras reported 981 tokens/sec on the 1T-parameter Kimi K2.6 model, a 6.7× speedup over the next GPU cloud, validated by an independent third party.
Cerebras Challenges Nvidia Inference Monopoly with Wafer-Scale Edge
Cerebras is challenging Nvidia's inference dominance with wafer-scale chips, as inference workloads surpass training in AI compute spend.