interconnect
30 articles about interconnect in AI news
NUS CIMERA Chip Cuts LLM Memory Wall with Compute-in-Interconnect
NUS researchers propose CIMERA, an LLM inference accelerator integrating compute-in-interconnect and memory to mitigate the memory wall, detailed in arXiv:2607.13649 (July 2026).
Silicon Photonics Hits 300-mm Wafer Scale for AI Interconnects
Silicon photonics moves to 300-mm wafers for AI interconnects, cutting cost per Gbps by ~30% and addressing bandwidth bottlenecks in 100,000+ GPU clusters.
Lightmatter Photonics Joins Nvidia NVLink Fusion for AI Interconnects
Lightmatter joins Nvidia NVLink Fusion with photonic interconnects. Nvidia Kyber rack delayed to 2028.
HPE Slingshot Leads Supercomputer Interconnects; China's 1.2 Exaflops
HPE's Slingshot tops supercomputer interconnects, but China's 1.2 exaflops machine steals the show, signaling a tightening race in HPC.
Google’s Virgo network interconnects 134K TPUv8t chips at 47 Pbps
Google's Virgo network interconnects 134,400 TPUv8t chips at 47 Pbps, targeting large-scale training clusters.
Nvidia Invests $2B in Marvell for NVLink Fusion Interconnect
Nvidia is investing $2 billion in Marvell Technology to deepen their partnership on NVLink Fusion, a new interconnect architecture for scaling AI clusters beyond current limits.
IOWN Forum Pushes All-Photonic WAN for AI Neocloud Interconnects
The IOWN Global Forum is focusing its optical networking tech on datacenter interconnects, aiming to let GPU 'neoclouds' and financial firms use cheaper, remote facilities without latency penalties for AI workloads.
AMD Backs UALink Open Interconnect to Challenge NVIDIA NVLink in AI
AMD is supporting the newly formed UALink Consortium, which aims to create an open standard for connecting AI accelerators. This move challenges NVIDIA's control over the critical NVLink technology that underpins its AI data center systems.
Crusoe, Lancium Build 1GW Texas AI Campus, Sidestepping Grid
Crusoe and Lancium announced a 1.0 GW AI data center campus in Texas, using gas-powered modules and grid-balancing software to bypass interconnection queues.
Upscale AI Raises $500M for AI-Native Networking Silicon
Upscale AI raised $500M for AI networking silicon, with Google Cloud as a strategic partner. The deal targets GPU cluster interconnect bottlenecks.
Intel Omni-Path Resurfaces as InfiniBand Rival for DoE Supercomputers
Intel's Omni-Path interconnect, revived by Cornelis Networks, will connect DoE supercomputers at 400Gbps as an InfiniBand alternative.
Google-Backed Tapestry Claims 811 Grid Apps Processed in Under an Hour
Google-backed Tapestry processed 811 PJM interconnection applications in under an hour, claiming to slash a months-long process to minutes.
Ethernet AI Switch Sales Double, InfiniBand Rebounds 22% in Q2
Ethernet AI switch sales doubled YoY as InfiniBand rebounded 22%. Ethernet now captures 41% of AI interconnect revenue, up from 28%.
Nvidia Partners Corning for US Fiber Manufacturing, Prepaying Billions
Nvidia partners Corning for US fiber manufacturing with multibillion-dollar prepayments, increasing domestic capacity by 50%+ for AI GPU cluster interconnects.
AI Data Centers Face 220GW Grid Jam, Power Infrastructure Becomes Bottleneck
PJM's 220GW interconnection queue shows AI data center growth is now constrained by power grid capacity, not compute. Hyperscalers face 3-7 year delays.
Nvidia Invests $2B in Marvell to Deepen NVLink Fusion Tie-Up
Nvidia invested $2B in Marvell to deepen NVLink Fusion partnership, integrating Marvell custom silicon into AI interconnect fabric.
Intel's UCIe-S Hits 48 Gb/s on 22nm, Beats 3nm EMIB
Intel demonstrated a UCIe-S die-to-die interconnect on 22nm hitting 48 Gb/s/lane over standard organic substrate, beating a 3nm EMIB design with 3× higher data rate and 2.8× higher bandwidth density. This signals a strategic shift away from EMIB for Intel's own products toward UCIe over substrate.
Google's Virgo Network Links 134,000 TPU v8 Chips with 47 Pbps Fabric
Google unveiled its Virgo networking stack for TPU v8, capable of linking 134,000 chips in a single fabric with 47 petabits/sec of bi-sectional bandwidth. This represents a massive scale-up in interconnect technology for large-scale AI model training.
Cisco Reveals Scale-Across GPU Networking Needs 14x DCI Bandwidth
Cisco's chief architect detailed the massive bandwidth requirements for connecting AI clusters via 'scale-across' GPU networking, which needs 14x the capacity of traditional data center interconnects. This shift is creating a multi-billion dollar market for 800G coherent pluggables and deep-buffered switches.
UALink 2.0 Spec Finalized, Aims to Challenge NVLink for AI Clusters
The UALink 2.0 interconnect specification has been finalized, providing a standardized way to link AI accelerators from AMD, Intel, and others. However, it lags behind NVIDIA's established NVLink technology in real-world deployment.
Nvidia's Silicon Photonics Roadmap Targets AI Data Center Bottlenecks
Nvidia is developing its own silicon photonics-based interconnects to address the growing data transfer bottleneck within AI data centers and supercomputers. This move is critical as AI model size and cluster scale continue to grow exponentially.
Nvidia Invests $2B in Marvell to Expand NVLink Fusion Chip Partnership
Nvidia is investing $2 billion in Marvell Technology to deepen their partnership on NVLink Fusion, a chip-to-chip interconnect crucial for scaling AI training clusters. This strategic move aims to secure supply and accelerate development of high-bandwidth links between GPUs and custom AI accelerators.
Open-Source AI Crew Replaces Notion, Obsidian with 8 Local Agents
A researcher has built a fully local, open-source system of 8 specialized AI agents that work together to manage an Obsidian vault—handling notes, inboxes, meetings, and deadlines. It replaces separate tools like Notion and inbox triagers with an autonomous, interconnected crew.
OpenAI's $20B Georgia Data Center Tests Gigawatt Buildout
OpenAI announced $20B Georgia data center. Gigawatt buildout faces execution test amid supply chain and power constraints.
Crusoe and ON.energy to Deploy 5 GW of AI UPS at Hyperscale Campuses
Crusoe and ON.energy will deploy 5 GW of gas-fired AI UPS with carbon capture at hyperscale campuses, bypassing grid constraints for AI training clusters.
Microsoft to Deploy AMD Helios Rack-Scale AI at Scale on Azure
Microsoft will deploy AMD's Helios rack-scale AI accelerator at scale on Azure, powered by MI455X GPUs and Epyc Venice CPUs. The move diversifies Azure's AI silicon beyond Nvidia.
China's AI ecosystem standardizes on MoE with wide expert parallelism
China's AI ecosystem standardizes on MoE with wide expert parallelism to survive on weaker NPUs. Hardware makers now design 'supernode' systems.
Musk Spent ~$1B on APR Energy to Power xAI, FTC Filing Reveals
Elon Musk spent ~$1B on APR Energy for 1 GW mobile turbine capacity to power xAI, per FTC filing. The deal gives xAI energy independence in the AI arms race.
Google Chooses Intel EMIB-T for 9th-Gen TPUs, Breaking TSMC's CoWoS Monopoly
Google picks Intel EMIB-T for 9th-gen TPU, breaking TSMC CoWoS monopoly. Move signals architectural bet on power integrity and reticle-free scaling.
New York pauses AI data centers >50 MW in first U.S. state ban
New York pauses permits for data centers over 50 MW for one year — first U.S. state ban on AI data centers. GEIS will set standards for grid, water, and community impacts.