chip packaging
27 articles about chip packaging in AI news
Cerebras Reengineers Mechanical Playbook for Wafer-Scale Chip Cooling
Cerebras disclosed three mechanical innovations—vertical power delivery, flexible interposers, and direct-impingement cooling—to prevent wafer-scale chips from cracking, rewriting engineering fundamentals.
The $500B AI Chip Bottleneck: One Material, One Supplier
A single Japanese chemical company supplies 98% of the thin-film material used in every AI chip on earth. NVIDIA is paying half the capex to expand supplier fabs as lead times stretch past 6 months.
Nvidia Invests $2B in Marvell to Expand NVLink Fusion Chip Partnership
Nvidia is investing $2 billion in Marvell Technology to deepen their partnership on NVLink Fusion, a chip-to-chip interconnect crucial for scaling AI training clusters. This strategic move aims to secure supply and accelerate development of high-bandwidth links between GPUs and custom AI accelerators.
TSMC's $56B 2026 CapEx Fuels AI Chip Race with 22 New Fabs
TSMC is constructing up to 22 advanced semiconductor fabs simultaneously, backed by a $52–56 billion capital expenditure plan for 2026. This unprecedented manufacturing scale is critical for producing the 2nm-and-below chips required by next-generation AI models.
Broadcom to Manufacture Google TPU Chips in Foundry Partnership
Google has licensed its Tensor Processing Unit (TPU) intellectual property to Broadcom for chip fabrication. This allows Google to earn from its IP while Broadcom manages the complex hardware build and networking integration.
The Invisible Dance: How AI Chip Manufacturing Relies on Microscopic Wire Bonding
High-speed semiconductor wire bonding creates thousands of electrical connections per minute using ultra-fine 25-micron wires. This critical but often overlooked process enables the AI chips powering today's most advanced systems.
China's Semiconductor Leaders Rally for National AI Chip Alliance Amid Tech War Escalation
China's top semiconductor executives have issued an unprecedented public call for a consolidated national effort to build AI chips, signaling a strategic shift toward self-reliance as U.S. export controls tighten. This coordinated push represents China's most direct response yet to technological containment efforts.
CNAS Report: AI Hits Silicon Wall as Chip Supply Trails $700B CapEx
CNAS report warns semiconductor manufacturing cannot keep pace with AI demand as hyperscalers plan $700B+ CapEx in 2026. Silicon replaces power as the near-term constraint.
AI Chip Capacity Crisis: 10GW Left Through 2030, Prices Up Double Digits
The AI accelerator market has only 10 gigawatts of capacity left for contract through 2030, with 100GW already under contract. Prices are rising double digits as one competitor has stopped taking orders entirely.
Aehr Test Systems Lands $41M AI Chip Order; H2 Bookings Top $92M
Aehr Test Systems received a record $41 million production order from a key hyperscale AI customer. Total bookings for the second half of its fiscal year exceeded $92 million, highlighting surging demand for semiconductor test and burn-in equipment.
Nvidia B200 Costs $6,400 to Produce, Gross Margin Hits 82%
Epoch AI estimates Nvidia's B200 GPU costs $5,700–$7,300 to produce, with HBM memory and advanced packaging accounting for two-thirds of the cost. At a $30k–$40k sale price, chip-level gross margins reach ~82%, though rack-scale margins may be lower.
Jensen Huang's 30-Year TSMC Battle: From 3D Graphics to AI GPUs
A 30-year-old comic shows Jensen Huang convincing TSMC to supply wafers for 3D graphics chips. Today, he's still fighting for wafer supply, but now for AI GPUs, alongside Broadcom, AMD, MediaTek, and Amazon.
Samsung Projects Record $14.6B Q1 Profit on 300% DRAM Price Surge
Samsung Electronics expects a record Q1 operating profit of 20 trillion won (~$14.6B), nearly triple YoY, fueled by soaring AI-driven demand and a 300% price increase for DRAM chips.
Google Books Intel for 3M+ TPUs in 2028 as TSMC CoWoS Hits Capacity Wall
Google booked Intel to package 3M+ TPUs in 2028 as TSMC CoWoS capacity caps out. SK hynix tests HBM on Intel EMIB, potentially unlocking Nvidia's Feynman architecture.
MLCC Shortage Threatens AI Server Ramp: Prices Hiking, Lead Times Stretching
MLCCs, cheap components stabilizing voltage in AI servers, face supply crunch as demand grows ~5x by CY27. Lead times stretch, prices hike, new lines take 2 years.
GUC, Wiwynn Partner on Silicon-to-System AI Infrastructure for Hyperscalers
GUC and Wiwynn partner on silicon-to-system AI infrastructure, integrating SoC design, optical I/O, and liquid cooling for hyperscalers.
Intel's UCIe-S Hits 48 Gb/s on 22nm, Beats 3nm EMIB
Intel demonstrated a UCIe-S die-to-die interconnect on 22nm hitting 48 Gb/s/lane over standard organic substrate, beating a 3nm EMIB design with 3× higher data rate and 2.8× higher bandwidth density. This signals a strategic shift away from EMIB for Intel's own products toward UCIe over substrate.
Microsoft's Fairwater AI Data Center Launches Early, Boosts Azure Capacity
Microsoft has launched its Fairwater AI data center ahead of schedule. The facility adds significant high-performance computing capacity to Azure's AI infrastructure, crucial for training and running large models.
Foxconn to Mass-Produce 10,000+ CPO Optical Switches for AI in Q3 2026
Foxconn's manufacturing arm will begin volume production of advanced co-packaged optics (CPO) switches in Q3 2026, targeting over 10,000 units. This move directly addresses the critical bandwidth and power bottlenecks in next-generation AI data center infrastructure.
Meta Expands Broadcom Partnership for Next-Gen AI Infrastructure
Meta is expanding its partnership with semiconductor giant Broadcom to co-develop its next-generation AI infrastructure. This move signals a continued, long-term commitment to custom silicon for AI training and inference.
AI-Powered Circuit Simulator Offers Free Hardware Prototyping
A new website provides a free, AI-assisted environment for designing and testing electronic circuits, featuring pre-built projects for learning. This lowers the barrier to entry for hardware prototyping and education.
Mac Studio AI Hardware Shortage Signals Shift to Cloud Rentals
Developers report a global shortage of high-memory Apple Silicon Macs, with 128GB Mac Studios unavailable worldwide. This pushes practitioners toward renting cloud H100 GPUs at ~$3/hr, marking a shift from the recent local AI trend.
VMLOps Publishes 2026 AI Engineer Roadmap for Software Engineers
VMLOps published a comprehensive 2026 roadmap detailing the skills and knowledge software engineers need to transition into AI engineering. The guide reflects the current industry demand for engineers who can build and deploy production AI systems.
Apple Reportedly Developing 'Balta' AI ASIC for Cloud Compute
A Morgan Stanley report indicates Apple is accelerating development of a custom ASIC, codenamed 'Balta,' for AI cloud and hybrid compute. This marks Apple's first known move to design silicon for its data centers, not just consumer devices.
Terafab's 1GW AI Compute Goal Requires Massive Fab Capacity
Analysis of Terafab's stated goals shows that achieving 1GW of AI compute would require approximately 190,000 wafer starts per month across logic and memory. This underscores the unprecedented scale of semiconductor manufacturing needed for future AI infrastructure.
AI Data Center HBM Shortage Intensifies as Samsung, SK Hynix, and Micron Struggle with Supply
AI data centers are aggressively stockpiling high-bandwidth memory (HBM), creating a supply crunch. Only three manufacturers—Samsung, SK Hynix, and Micron—can produce this critical component for AI servers.
Apple Announces Plans to Increase US iPhone Parts Manufacturing, Continuing Supply Chain Diversification
Apple has announced plans to manufacture more iPhone components within the United States. This continues a multi-year strategy to diversify its supply chain away from concentrated geographic regions.