wafer scale
30 articles about wafer scale in AI news
Silicon Photonics Hits 300-mm Wafer Scale for AI Interconnects
Silicon photonics moves to 300-mm wafers for AI interconnects, cutting cost per Gbps by ~30% and addressing bandwidth bottlenecks in 100,000+ GPU clusters.
Cerebras Reengineers Mechanical Playbook for Wafer-Scale Chip Cooling
Cerebras disclosed three mechanical innovations—vertical power delivery, flexible interposers, and direct-impingement cooling—to prevent wafer-scale chips from cracking, rewriting engineering fundamentals.
Cerebras Challenges Nvidia Inference Monopoly with Wafer-Scale Edge
Cerebras is challenging Nvidia's inference dominance with wafer-scale chips, as inference workloads surpass training in AI compute spend.
Cerebra's Tokenomics Bet: AWS, OpenAI Deals and Wafer-Scale Edge
Cerebra's tokenomics pricing and AWS/OpenAI partnerships challenge NVIDIA's inference dominance, offering a 5x cost reduction per token via its wafer-scale architecture.
Cerebras WSE-3 Claims 10x Training Speed Over Nvidia H100 on GPT-Scale Model
Cerebras claims 10x training speed over Nvidia H100 for GPT-3-scale models using WSE-3. Benchmark lacks power and cost data, limiting independent verification.
MITRE-Led Team Monolithically Integrates Piezo-Optomechanical Photonics
MITRE-led team demonstrated first monolithic CMOS platform for piezo-optomechanical photonics, achieving wafer-scale integration with 2.3x lower loss and 40% better bandwidth.
Cerebras, Flex Expand CS-3 Production 7x at Milpitas Facility
Cerebras and Flex expand CS-3 production 7x at Milpitas facility. The partnership keeps wafer-scale AI manufacturing in the U.S. as Nvidia faces delays.
Cerebras Claims Performance Parity With Nvidia H100 on AI Training
Cerebras claims wafer-scale chips match Nvidia H100 on AI training performance per watt, challenging Nvidia's dominance.
Cerebras IPO Challenges GPU Scaling Orthodoxy
Cerebras filed for IPO on April 21, betting wafer-scale chips can disrupt Nvidia's GPU cluster model for AI workloads.
Terafab's 1GW AI Compute Goal Requires Massive Fab Capacity
Analysis of Terafab's stated goals shows that achieving 1GW of AI compute would require approximately 190,000 wafer starts per month across logic and memory. This underscores the unprecedented scale of semiconductor manufacturing needed for future AI infrastructure.
Cerebras' Strategic Partnership Yields Breakthrough AI Training Results
Cerebras Systems' partnership with Abu Dhabi's G42 has produced remarkable AI training benchmarks, achieving results 100x faster than traditional GPU clusters. The collaboration demonstrates the viability of wafer-scale computing for large language model development.
Nvidia B200 Costs $6,400 to Produce, Gross Margin Hits 82%
Epoch AI estimates Nvidia's B200 GPU costs $5,700–$7,300 to produce, with HBM memory and advanced packaging accounting for two-thirds of the cost. At a $30k–$40k sale price, chip-level gross margins reach ~82%, though rack-scale margins may be lower.
Jensen Huang's 30-Year TSMC Battle: From 3D Graphics to AI GPUs
A 30-year-old comic shows Jensen Huang convincing TSMC to supply wafers for 3D graphics chips. Today, he's still fighting for wafer supply, but now for AI GPUs, alongside Broadcom, AMD, MediaTek, and Amazon.
Google's Virgo Network Links 134,000 TPU v8 Chips with 47 Pbps Fabric
Google unveiled its Virgo networking stack for TPU v8, capable of linking 134,000 chips in a single fabric with 47 petabits/sec of bi-sectional bandwidth. This represents a massive scale-up in interconnect technology for large-scale AI model training.
Nvidia's Silicon Photonics Roadmap Targets AI Data Center Bottlenecks
Nvidia is developing its own silicon photonics-based interconnects to address the growing data transfer bottleneck within AI data centers and supercomputers. This move is critical as AI model size and cluster scale continue to grow exponentially.
Aehr Test Systems Lands $41M AI Chip Order; H2 Bookings Top $92M
Aehr Test Systems received a record $41 million production order from a key hyperscale AI customer. Total bookings for the second half of its fiscal year exceeded $92 million, highlighting surging demand for semiconductor test and burn-in equipment.
TSMC's $56B 2026 CapEx Fuels AI Chip Race with 22 New Fabs
TSMC is constructing up to 22 advanced semiconductor fabs simultaneously, backed by a $52–56 billion capital expenditure plan for 2026. This unprecedented manufacturing scale is critical for producing the 2nm-and-below chips required by next-generation AI models.
Nvidia's Groq Ramps Up AI Chip Production with Samsung in Major Partnership Expansion
Nvidia's recent acquisition Groq has significantly expanded its partnership with Samsung, increasing chip orders from 9,000 to 30,000 wafers. This massive production boost signals accelerated development of Groq's specialized AI inference processors amid growing market demand.
AMD-Cerebras Disaggregated Inference: 5× T/s/W, Prompt vs. Decode Split
AMD and Cerebras launched a disaggregated inference platform splitting prompt processing on Helios from decode on WSE, claiming up to 5× T/s/W.
Theta-TaN Metal Hits 1,100 W/mK Thermal Conductivity, 3× Copper
UCLA and Tohoku University created theta-TaN with 1,100 W/mK thermal conductivity, 3× copper, approaching diamond-level heat dissipation for AI chip packaging.
GPT-5.6 Sol on Cerebras Hits 750 Token/s
GPT-5.6 Sol on Cerebras claimed at 750 token/s, but no official data or model release exists. Unverified claim needs vendor confirmation.
SambaNova Hits 850 t/s on MiniMax M2.7 via Hybrid H200-RDU Inferencing
SambaNovaAI achieved 850 t/s on MiniMax M2.7 by pairing H200 GPUs for prefill with SN50 RDUs for decode at RAISE Paris.
China PLP System Passes Validation at 510×515mm Panel Size
CFMEE validated a 510×515mm PLP system for AI chip packaging, challenging TSMC and Intel. The system targets HBM and AI accelerators, with potential 30% cost savings.
Qualcomm Taps TSMC for 3nm/2nm Dragonfly C100 CPUs, AI300 Accelerators
TSMC to fab Qualcomm's Dragonfly C100 and AI300 chips on 3nm/2nm nodes. The move challenges NVIDIA in data center AI, but timelines and performance remain undisclosed.
TSMC Cuts 28nm Output 25%+ as Advanced Node Push Accelerates
TSMC cut 28nm output over 25% since early 2026, reallocating to advanced nodes as AI demand surges. Mature node revenue share likely to shrink further.
Nvidia Commits $6.5B to Photonics in Supply Chain Bet on AI's Next Bottleneck
Nvidia has invested over $6.5 billion across four photonics suppliers since March 2026, pairing equity stakes with multi-billion-dollar purchase commitments. The deals coincide with capacity expansion announcements from Coherent, Nokia, and Japan's JX Advanced Metals, and signal that optical interco
Amazon Opens Trainium Chips to Outside Data Centers, Targeting Nvidia's Core Business
AWS AI chief Peter DeSantis confirmed Amazon is negotiating to sell Trainium chips externally for the first time, backed by Andy Jassy's estimate of a $50B annual revenue potential. With Trainium3 sold out, Trainium4 pre-booked, and Anthropic and OpenAI already running gigawatts of Trainium capacity
Google Books Intel for 3M+ TPUs in 2028 as TSMC CoWoS Hits Capacity Wall
Google booked Intel to package 3M+ TPUs in 2028 as TSMC CoWoS capacity caps out. SK hynix tests HBM on Intel EMIB, potentially unlocking Nvidia's Feynman architecture.
Memory Supply Squeeze Hits Non-AI Sectors as DRAM Prices Double
DRAM prices surged 93-98% QoQ in Q1 2026 as AI data centers consume fab capacity, nine industry groups warned the Trump administration on June 3, threatening supply for automotive, telecom, and medical devices.
SemiAnalysis: N3 chip demand far outstrips current consensus estimates
SemiAnalysis argues N3 chip demand far exceeds consensus accelerator models, implying a structural silicon shortage not priced by markets.